Seagate Internship 2024 | Freshers must apply

Seagate Internship 2024 | Freshers must apply
source: www.seagate.com

Seagate Internship 2024 | Freshers must apply: Hiring Intern – VLSI & Intern DI – Intern VLSI DV

 Seagate Internship 2024 | Freshers must apply: hiring freshers for VLSI & Intern DI – Intern VLSI DV. Candidates with Bachelor’s/Master’s Degree are eligible to apply. The detailed eligibility and application process are given below.

Details About Seagate Internship 2024 | Freshers must apply:

Company Website : www.seagate.com

Job Role: Intern – VLSI, Intern – VLSI DI & Intern – DV

Qualification: Bachelor’s/ Master’s Degree

Job TitleSeagate Internship 2024 | Freshers must apply
DescriptionBachelor’s/ Master’s Degree
Work LocationPune – IN
Employment TypeFULL TIME

Batch: Recent Batches

Experience: Freshers

Salary: ₹ 4 LPA (Expected)

Job Location: Pune

Last Date: ASAP

About our group:

 Seagate Technology is seeking for an upcoming motivated engineer for Product Test Engineer to perform all aspects of product and test engineering including working with test functions across different geographic locations as well as with offshore OSAT (Offshore Assembling Test) locations. This role will report into Director for Hardware ATE Test Team in  Seagate’s VLSI Engineering Group.

Details About the role – you will for Seagate Internship:

Develop Test Programs and debug SoC controllers for HDD and/or SSD

Perform data collection, analysis and characterization report generation of all products

Design of reliability hardware working in close coordination with TE

Deploying products in to HVM (High Volume Manufacturing) at OSAT locations

Work with offshore product engineers for release and manage of ATE (Automated Test Experiments) test programs at production test facilities

Conduct high volume test data analysis using data analysis tools

Work closely with test development engineers to improve production yield, test related issues and cycle times improvementsSeagate Internship 2024 | Freshers must apply

About you:

Excellent English written and oral communication skills

Having the flexibility to attend meetings with global team (Taiwan, India and USA) in different time zones

Basic understanding of Semiconductor Design For Test (DFT) techniques such as ATPG, MBIST, loop back testing of high performance serdes etc.

Your experience includes:

Skill in programming language C, C++, shell script languages like PERL, AWK, and Python

Exposure or Experience in Semiconductor industry

Basic understanding of Semiconductor Design For Test (DFT) techniques such as ATPG, MBIST, loop back testing of high performance serdes etc.

Experience with Statistical Data Processing, DOEs (Design of experiments), problem

Solving methodologies, demonstrated decision making skills, cost reduction, and yield enhancement is a plus

Exposure to Automate Test Equipment (ATE) like Verigy 93000 Digital test platform etc.

Details About the Intern – VLSI DI role –  you will:

Be able to work on block level Physical Design implementation using EDA tools for floorplanning, placement and timing analysis

Understand Semicustom IC design flow using IP libraries, concepts of Verilog netlist, meaning of timing constraints and QOR checks

Work on Physical design tasks including floor-planning, placement, clock tree synthesis, routing, timing analysis and equivalence checking for designs

Work on Timing analysis for sign-off corners and modes, report generation, analysis of the reports and suggesting timing/DRC fixes to fix the violations

Complete internship project as per plan

About you at  Seagate Internship 2024 | Freshers must apply:

Knowledge of ASIC design flow and tools

Good understanding of Circuit design and Logic design

Good understanding of analog circuit design and concepts

Good understanding of timing concepts like setup time, hold time requirements, calculations of maximum

Understanding Frequency of circuit operations, effect of transition and load on circuit performance and power

Basic understanding of CMOS fabrication process

Basic understanding of layout design for CMOS and BJT

Basic understanding of power dissipation in different types of circuits

Self-motivated & a strong team player

Strong analytical skills

Ability to quickly learn new tools and technologies

Your experience includes for  Seagate Internship 2024 | Freshers must apply:

ASIC design flow, basic EDA tools for Physical design implementation

Place and Route, Timing Analysis, Equivalence check

Perl, Tcl, Shell or other scripting languages

About the role Intern – VLSI DV – you will:

Receive training on Functional Verification Methodologies at IP and SoC level using

System Verilog and UVM

Be able to work on verifying designs using Synopsys Simulation tools

Develop Test-bench & Reference models in IP & SoC level verification environments

Document and Implement Verification Plans

Work closely with design engineers to create constrained random based test-benches and

test cases to meet the required functional and code coverage metrics

Debug and help resolve test failures

Create reusable verification environments to be used across multiple teams

Complete internship project as per plan

About you at  Seagate Internship 2024 | Freshers must apply:

Knowledge of ASIC design flow and tools

Good understanding of Circuit design, Logic design, Setup time, Hold time, Combinatorial

and Sequential circuits, CMOS and Power consumption

Self-motivated & a strong team player

Strong debug and analytical skills

Ability to quickly learn new tools and technologies

Your experience includes for  Seagate Internship 2024 | Freshers must apply:

Knowledge of Verilog, SystemVerilog, VHDL, UVM or other verification methodologies

Knowledge of C++ or other OOP languages with strong background in OOP concepts

Perl, Tcl, Shell or other scripting languages

Understanding of VLSI engineering cycle

How to Apply For Seagate Internship 2024 | Freshers must apply?

All interested and eligible candidates can apply for  Seagate Internship 2024 online by the following link as soon as possible.

Apply Link for VLSI:  Click here

Apply Link for VLSI DI:  Click here

Apply Link for VLSI DV:  Click here

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