Pipeline also known as a data pipeline, is a set of data processing elements connected in series, where the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion. Some amount of buffer storage is often inserted between elements.

Pipelining is a commonly using concept in everyday life. For example, in the assembly line of a car factory, each specific task—such as installing the engine, installing the hood, and installing the wheels—is often done by a separate work station. The stations carry out their tasks in parallel, each on a different car. Once a car has had one task performed, it moves to the next station. Variations in the time need to complete the tasks can be accommodating by “buffering” (holding one or more cars in a space between the stations) and/or by “stalling” (temporarily halting the upstream stations), until the next station becomes available.

Suppose that assembling one car requires three tasks that take 20, 10, and 15 minutes, respectively. Then, if all three tasks were perform by a single station, the factory would output one car every 45 minutes. By using a pipeline of three stations, the factory would output the first car in 45 minutes, and then a new one every 20 minutes.

As this example shows, pipelining does not decrease the latency, that is, the total time for one item to go through the whole system. It does however increase the system’s throughput, that is, the rate at which new items are process after the first one.

What are the stages of pipelining?

In the early days of computer hardware, Reduced Instruction Set Computer Central Processing Units (RISC CPUs) was design to execute one instruction per cycle, five stages in total. Those stages are, Fetch, Decode, Execute, Memory, and Write.

What are the types of pipeline?

  • Arithmetic Pipelining.
  • Instruction Pipelining.
  • Processor Pipelining.
  • Uni-function
  • Static vs Dynamic Pipelining.
  • Scalar vs Vector Pipelining.

What are advantages of Pipelining?

Increase in the number of pipeline stages increases the number of instructions executed simultaneously. Faster ALU can design when pipelining is use. Pipelined CPU’s works at higher clock frequencies than the RAM. Pipelining increases the overall performance of the CPU.

What are disadvantages of pipelining?

  1. Designing of the pipelined processor is complex.
  2. Instruction latency increases in pipelined processors.
  3. The throughput of a pipelined processor is difficult to predict.
  4. The longer the pipeline, worse the problem of hazard for branch instructions.

What is decode in pipeline?

The decode stage of the pipeline checks for IPC messages from the firmware. If a POKE or PEEK message is receive, a store or load cycle is execute instead of NOP. When a load cycle completes, a PEEKREPLY message with the result of the load is transfer back to the firmware program.

Why do we need pipelining?

Pipelining keeps all portions of the processor occupied and increases the amount of useful work the processor can do in a given time. Pipelining typically reduces the processor’s cycle time and increases the throughput of instructions.

How pipelining improve the performance of a computer?

Super pipelining improves the performance by decomposing the long latency stages (such as memory access stages) of a pipeline into several shorter stages, thereby possibly increasing the number of instructions running in parallel at each cycle.

Does pipeline reduce latency?

Pipelining reduces the cycle time to the length of the longest stage plus the register delay. Latency becomes CT*N where N is the number of stages as one instruction will need to go through each of the stages and each stage takes one cycle.

How does pipelining affect clock frequency?

It increases average throughput for the same clock speed, which is exactly the same thing as decreasing average CPI. Or it lets you increase the clock speed if your CPU’s clock was so slow that it could do everything for a whole instruction in one clock cycle.